1. Field of the Invention
The present invention relates to the field of mixed signal integrated circuits and, more particularly, to gain calibration of an analog-to-digital converter.
2. Background of the Related Art
The use of analog-to-digital converters (A/D converters or ADCs) to convert analog signals into digital signals is well known in the art. State-of-the-art practice is to fabricate an ADC on a single integrated circuit chip. Generally, an ADC samples an analog signal at a sampling rate which is twice the highest frequency component being sampled. This is known as the Nyquist rate. The sampled signal is processed and converted into a digital format for output from the converter.
Another type of ADC employs an oversampling technique in which the analog input signal is sampled at a much higher rate than the Nyquist rate. The higher sampling rate improves the performance of the ADC for signal conversion and processing. One commonly used oversampling type of ADC uses a delta-sigma (.DELTA..SIGMA.) modulator for oversampling the analog input. The oversampled output of the .DELTA..SIGMA. modulator is coupled to a decimator, which employs a low-pass filtering technique to extract the lower frequency components to generate a converted digital output signal at the Nyquist rate.
It is appreciated that ADCs are mixed-signal devices that require fine tuning to produce an accurate digital output for a given analog input. With one-to-one scaling, a full analog positive input signal (peak signal) should generate a full digital output word (highest digital value). The minimum analog input should also have the minimum digital output. It is also desirable for the conversion process or function to have a linear response between the minimum and maximum outputs. However, since perfect converters cannot be fabricated, mainly due to manufacturing imperfections and component mis-match, calibration procedures are typically required in ADCs.
Two common errors in ADCs, including ADCs using a .DELTA..SIGMA. modulator, are offset and gain errors. The offset error (or offset) is the difference in the digital output value from the desired value of zero, when there is zero analog input. The gain error is the difference in the actual digital output value from the desired digital output value, with the offset error compensated. That is, although the offset is zero, the gain error can cause the ADC to produce a digital value which fails to accurately track the analog input. Accordingly, offset and gain calibration are used to adjust the offset and gain errors inherent in the ADC.
Typically, offset calibration is performed first. With zero analog input, the digital output (referred to as the offset value) is noted and retained. Subsequently, when digital outputs are obtained during normal ADC operations, the offset (D.sub.OFFSET) value is subtracted from the actual measured digital output to obtain the correct digital value. Then, gain calibration is utilized to adjust the gain so that a proper gain response is obtained in the ADC. Typically, for gain calibration, a known voltage value is input to the ADC and the actual measured digital output value is compared to the value which should be generated for the known input, after subtracting the offset. A known calibration voltage or a reference voltage is utilized at the input. Thus, if an analog full-scale (A.sub.FS) value is input, then the expected value would be a digital full-scale (D.sub.FS) value. If the measured digital value with A.sub.FS as input is defined as D.sub.MEAS, then the gain error is defined as ((D.sub.MEAS -D.sub.OFFSET)/D.sub.FS)-1, where D.sub.OFFSET is the previously measured offset error. Subsequently during normal operations, the digital output value is scaled by the factor D.sub.FS /D.sub.MEAS to provide the correct gain, after first correcting the offset.
The present invention describes a technique of performing gain calibration on an ADC having a differential input, in which offset shift introduced by a common mode variation is nullified.